The costs for producing reticles have increased due to miniaturization of semiconductor integrated circuit device over these recent years. Therefore, a multi-chip reticle adapted to expose different types of chips with the similar reticle has been proposed. For instance, a multi-die reticle adapted to expose chips of different types and sizes with the similar reticle has been proposed.
FIG. 16 illustrates a multi-die reticle, which includes a plurality of main chip regions M1, M2, and M3. A region outside the main chip regions M1 to M3 defines a non-layout region NL, which does not form a chip.
Each of the main chip regions M1, M2, and M3 is a region in which a pattern for exposing a main chip is formed. In each of the main chip regions M1, M2, and M3, an exposure pattern for exposing the desired device pattern on a substrate is formed. Further, an exposure pattern for exposing a large number of wiring layers is also formed.
The non-layout region NL does not include an exposure pattern for exposing a device pattern and an exposure pattern for exposing wiring layers. In a region of a substrate that corresponds to the non-layout region NL, inter-wiring insulation layers are superimposed but wiring layers are not superimposed.
FIG. 15 illustrates the cross-section of main chip regions and a non-layout region in a wafer substrate W manufactured with the multi-die reticle of FIG. 16. Points A and B in FIG. 15 respectively correspond to points A and B through which line C-C extends in FIG. 16. In the main chip regions M1 and M3 of the wafer substrate W, a plurality of wiring layers LA, LB, and LC are formed, and metal lines ML are formed in each of the wiring layers LA to LC. In the non-layout region NL, the plurality of wiring layers LA to LC each include an inter-wiring insulation layer. That is, in the non-layout region NL of the wafer substrate W, a metal line ML is not formed in the wiring layers LA to LC.
FIG. 17 illustrates a graphical image of the multi-die reticle. Main chip regions M of various types and non-layout regions NL of various shapes are scattered in the multi-die reticle. An operation of generating scribe data included in a process for generating CAD data (also referred to as reticle data) used to form the multi-die reticle is described with reference to FIG. 18.
First, process specification data and process pattern mark data are retrieved to generate data for forming a scribe line (operations S1, S2). Marks (alignment marks, inspection marks, etc.) are laid out on the scribe line (operation S3).
When each mark is laid out on the scribe line, a dummy pattern is arranged on the scribe line so that the scribe line and the main chip region may be planarized when polished in the subsequent CMP operation (operations S4, S5). The generated CAD data is then output (operation S6), and the data generation operation is terminated.
If each mark is not laid out on the scribe line in operation S4, an error output is generated (operation S7), and the data generation operation is terminated.
Through such processing, the marks are laid out on the scribe line, and a scribe region is planarized with a main chip region.